Electronic clock

ABSTRACT

The invention provides a rechargeable electronic timepiece that restarts the operation of a clock circuit by inputting a power source, thereby securely confirming the clock operation. The electronic timepiece includes a first power source ( 2 ), a clock circuit ( 8 ) connected to the first power source, a power source input detecting circuit ( 86 ) for detecting an input of a second power source ( 3 ), a switch circuit ( 7, 9 ) for connecting the first power source and the second power source, and a control circuit ( 87 ) for controlling the switch circuit to connect the first power source and the second power source so that the first power source is charged by the second power source thereby operating the clock circuit when the power source input detecting circuit detects an input of the second power source.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to an electronic timepiece having acontrol circuit for a power source switch. Particularly, the presentinvention relates to an electronic timepiece capable of quickly startinga clock circuit when power is supplied, during inspection, in the middleof an assembly process.

2. Description of the Related Art

An electronic timepiece, particularly a rechargeable electronictimepiece, can use a small-capacity capacitor and a large-capacitycapacitor in some cases. In this case, the small-capacity capacitor isused to operate a clock circuit of the electronic timepiece until thelarge-capacity capacitor is charged to a level at which thelarge-capacity capacitor can normally operate the clock circuit of theelectronic timepiece. When a voltage detecting circuit detects that thelarge-capacity capacitor is sufficiently charged, the power source, tosupply power to the electronic timepiece is switched from thesmall-capacity capacitor to the large-capacity capacitor. When a voltageof the large-capacity capacitor drops, the power source for supplyingpower to the electronic timepiece is switched from the large-capacitycapacitor to the small-capacity capacitor (refer to Japanese PatentApplication Unexamined Publication No. 4-81754, FIG. 1 on page 5).

In general, this type of rechargeable electronic timepiece has a solarcell or the like as a power source, and charges the large-capacitycapacitor and the small-capacity capacitor using this solar cell as thepower source. However, during the assembly process in a plant or duringthe disassembly and cleaning at a retail shop, it is often necessary toconfirm the operation of the clock circuit before the solar cell beforethe power source is built into or restored to the electronic timepiece.In this case, the large-capacity capacitor (usually a secondary cell)not connected to the solar cell is built into the electronic timepiece,thereby operating the clock circuit by using the power charged in thislarge-capacity capacitor.

A conventional technique is explained below with reference to FIG. 15.FIG. 15 is a block diagram of a conventional rechargeable electronictimepiece. In FIG. 15, a reference numeral 1 denotes power generatingmeans, which is a solar cell according to the present conventionalexample. A reference numeral 2 denotes first storage means that storesenergy of the power generating means 1, and operates a clock circuit. Acapacitor is used for the first storage means, according to the presentconventional example. A reference numeral 3 denotes second storage meansthat stores energy of the first power generating means 1, and dischargesenergy to the first storage means 2 when the power generating means 1 isnot generating power. A secondary cell is used for the second storagemeans, according to the present conventional example. In general, a cellhaving a smaller capacity than that of the secondary cell 3 is used forthe capacitor 2.

Reference numerals 4 and 5 denote backflow preventing diodes thatprevent a backflow of the energy stored in the first storage means 2 andthe second storage means 3 to the power generating means 1, when thepower generating means 1 is not generating power, or when the powergenerating means 1 is not generating electromotive force. A referencenumeral 6 denotes a switch for turning on so as to charge powergeneration energy of the power generating means 1 to the second storagemeans 3. This switch 6 consists of an N-channel transistor 61, accordingto the present conventional example. A reference numeral 7 denotes aswitch to connect the first storage means 2 and the second storage means3, in parallel, when the second storage means 3 is sufficiently charged.According to the present conventional example, the switch 7 consists ofa backward N-channel transistor 71 and a forward N-channel transistor72.

A reference numeral 8 denotes a clock circuit. The clock circuit 8includes: an oscillating circuit 81; an oscillation halt detectingcircuit 82 that detects whether the oscillating circuit 81 isoscillating; a frequency-dividing circuit 83 that divides a frequency ofa signal of the oscillating circuit 81; a waveform shaping circuit 84that generates a desired signal using a signal of the frequency-dividingcircuit 83; and a cell voltage detecting circuit 85 that detects avoltage of the second storage means 3. The clock circuit 8 also includesa digital frequency controlling circuit and a motor driving circuit,which are omitted from the present explanation.

The operation of the conventional rechargeable electronic timepieceshown in the block diagram in FIG. 15 is explained next. When the secondstorage means 3 is not sufficiently charged, the cell voltage detectingcircuit 85 detects that the voltage of the second storage means 3 islow, and turns off the switch 7. The waveform shaping circuit 84controls the switch 6 to be repeatedly turned on and off every second.While the switch 6 is off, the power generation energy of the powergenerating means 1 is charged to the first storage means 2. While theswitch 6 is on, the power generation energy of the power generatingmeans 1 is charged to the second storage means 3.

When the voltage of the second storage means 3 rises after the secondstorage means is charged by the power generating means 1 when the secondstorage means 3 is not sufficiently charged, the cell voltage detectingcircuit 85 detects the rise of the voltage of the second storage means3, and turns on the switch 7. As a result, the first storage means 2 andthe second storage means 3 are connected in parallel. Therefore, thepower generating means 1 simultaneously charges the first storage means2 and the second storage means 3, regardless of whether the switch 6 ison or off. In the state that the first storage means 2 and the secondstorage means 3 are connected in parallel, the second storage means 3replenishes energy to the first storage means 2 even when the powergenerating means 1 does not generate power. Therefore, the clock circuit8 can continue in operation.

When a state that the power generating means 1 does not generate powercontinues, the energy stored in the second storage means 3 decreases.Then, the cell voltage detecting circuit 85 detects a reduction in thevoltage of the second storage means 3, and turns off the switch 7. As aresult, the power source of the clock circuit 8 is switched to the firststorage means 2. When the state that the power generating means 1 doesnot generate power further continues, the energy stored in the firststorage means 2 is consumed, which lowers the voltage, and halts theoperation of the oscillating circuit 81. At the same time, the waveformshaping circuit 84 halts the operation, and the switch 6 is turned off.

When the state that the power generating means 1 does not generate powerfurther continues, the energy stored in the first storage means 2further decreases due to a leakage inside the clock circuit 8 or thelike, and the voltage of the first storage means 2 comes close to 0 volt(GND). Then, there is a risk that a potential of an L level, that thewaveform shaping circuit 84 and the cell voltage detecting circuit 85are outputting to turn off the switch 6 and the switch 7, is recognizedas an H level, and the switch 6 and the switch 7 are turned on. In orderto avoid this risk, the waveform shaping circuit 84 and the cell voltagedetecting circuit 85 are configured to output the L level of a bulkpotential of respective N-channel transistors, thereby turning off theswitches, while the oscillation halt detecting circuit 82 is detectingthe oscillation halt.

As explained above, when the clock circuit 8 has halted the operation,the switch 7 is in the off state, and the power source of the clockcircuit is set to the first storage means 2. Therefore, the clockcircuit 8 starts operating again when energy is stored in the firststorage means 2, that is, when the power generating means 1 starts powergeneration. Because the switch 6 and the switch 7 are in the off state,when the power generating means 1 starts generating power, the powerenergy generated by the power generating means 1 is stored into thefirst storage means 2. When the voltage of the first storage means 2exceeds the operating voltage of the oscillating circuit 81, theoscillating circuit 81 starts operating, and the switch 6 and the switch7 can be controlled.

The above explains the operations of the power generating means 1 andthe first and the second storage means 2 and 3, in the state that thepower generating means (i.e., the solar cell) 1 is connected to thecircuit. However, as explained above, it is often necessary to confirmthe operation of the clock circuit before the power generating means 1is connected to the first storage means 2 or the second storage means 3in the middle of the assembly process in the plant.

In this case, at the beginning, the second storage means 3 that ischarged to some extent beforehand is put into the electronic timepiece(i.e., connected to or built in the circuit of the electronictimepiece). Before the power generating means 1 is connected to thecircuit, the clock circuit 8 is in a non-driven state as a matter ofcourse. When the second storage means 3 is input to the electronictimepiece, it becomes possible to charge the first storage means 2.However, because the clock circuit 8 is not operating, the cell voltagedetecting circuit 85 is in the non-driven state. Therefore, the firststorage means 2 as the power source of the clock circuit 8 is separatedfrom the second storage means 3. To overcome this difficulty, both sidesof the switch 7 are connected with a conductive pin to compulsivelycharge the first storage means 2, thereby driving the clock circuit 8.As an alternative method, it is necessary to take the trouble ofconnecting the power generating means (i.e., the solar cell) 1 to thecircuit to secure a power source, thereby driving the clock circuit 8.According to the above method, when the voltage of the first storagemeans 2 becomes equal to or higher than a constant voltage, the clockcircuit 8 starts operating. Thereafter, the operation of the clockcircuit is confirmed. For example, the power consumption is checked.

As described above, the conventional chargeable electronic timepiece hasthe following problems.

When the cell voltage of the first storage means 2 is insufficient, thefirst storage means 2 must be charged to operate the clock circuit 8.For example, in order to confirm whether the clock circuit 8 operates inthe middle of the assembly process of the production line in the plant,it is necessary to (1) compulsively charge the first storage means 2 byputting the second storage means 3 into the electronic timepiece, or (2)charge the first storage means 2 by connecting the power generating unit(i.e., the solar cell) 1 to the circuit.

Particularly at the time of measuring power consumption of the clockcircuit 8 in the production line, an ammeter is usually connected to aterminal of the second storage means 3. However, the clock circuit 8does not operate until when the first storage means 2 as the powersource of the clock circuit 8 is charged. Therefore, it is necessary totake the trouble to compulsively charge the first storage means 2. Totake time in charging the first storage means 2 in this way is verytroublesome. This point similarly applies to the disassembly and repairof the electronic timepiece.

SUMMARY OF THE INVENTION

It is an object of the present invention to provide a (rechargeable)electronic timepiece that can solve the above problems, can securelystart operating a clock system by simply putting a secondary cell intothe electronic timepiece, and can confirm the operation of a clockcircuit, such as measuring power consumption, in a short time.

In order to achieve the above object, the present invention provides anelectronic timepiece including a first power source, a clock circuitconnected to the first power source, a power source input detectingcircuit for detecting an input of a second power source, a switchcircuit for connecting the first power source and the second powersource, and a control circuit for controlling the switch circuit toconnect the first power source and the second power source so that thefirst power source is charged by the second power source therebyoperating the clock circuit when the power source input detectingcircuit detects an input of the second power source. Because theelectronic timepiece is configured to turn on the switch by detectingthe input of the second power source, thereby supplying power to theclock circuit, the electronic timepiece can operate the clock circuit ina halted state even if the power generating means generates power.Further, because the electronic timepiece is configured to turn on theswitch by detecting the input of the second power source, therebysupplying power to the clock circuit, the electronic timepiece canoperate the clock circuit in a halted state even if the first powersource has no stored energy.

In the electronic timepiece according to the present invention, it ispreferable that the second power source has a capacity larger than thatof the first power source.

In the electronic timepiece according to the present invention, it ispreferable that the switch circuit has a first switch that connects thefirst power source and the second power source in parallel, and a secondswitch that is connected in parallel to the first switch, and that whenthe power source input detecting circuit detects the input of the secondpower source, the control circuit turns on the second switch to connectthe first power source and the second power source.

It is preferable that the electronic timepiece according to the presentinvention further includes a power generator and voltage detector forturning on the first switch when the power generator sufficientlycharges the second power source.

In the electronic timepiece according to the present invention, it ispreferable that the control circuit is controlled by the clock circuit.

In the electronic timepiece according to the present invention, it ispreferable that the control circuit is controlled by the clock circuitto turn off the second switch when the oscillating circuit startsoscillating after the second switch is turned on. Because the electronictimepiece is configured such that the switch is turned off after theoscillating circuit starts oscillating, the electronic timepiece cancarry out the normal operation after the switch is turned off.

In the electronic timepiece according to the present invention, it ispreferable that the control circuit turns off the second switch after alapse of a predetermined time after the second switch is turned on.Because the electronic timepiece is configured such that the switch isturned off after a lapse of sufficient time after the oscillatingcircuit starts oscillating, the clock circuit can be securely operatedafter the power source is input.

In the electronic timepiece according to the present invention, it ispreferable that the control circuit includes clocking means, and thatwhen the clocking means runs for a predetermined time, the controlcircuit turns off the second switch. Because the electronic timepiece isconfigured such that the switch is turned off after a lapse ofsufficient time, the clock circuit can be operated securely.

In the electronic timepiece according to the present invention, it ispreferable that the control circuit is controlled by the clock circuitto turn off the second switch after a lapse of a predetermined timeafter the oscillating circuit starts oscillating after the second switchis turned on. Because the electronic timepiece is configured such thatthe switch is turned off after a lapse of sufficient time after theoscillating circuit starts oscillating, the clock circuit can besecurely operated after the power source is input.

In the electronic timepiece according to the present invention, it ispreferable that the control circuit controls to turn off the secondswitch when it is detected that the power generator generates powerafter the second switch is turned on. Because the electronic timepieceis configured such that the switch remains in the off state when thepower generator is generating power, the electronic timepiece canquickly starts running after the power generation is started.

It is preferable that the electronic timepiece according to the presentinvention further includes a comparator circuit that operates so as notto turn on the second switch when the voltage of the second power sourceis at or below a predetermined voltage. Because the electronic timepieceis configured such that the switch is not turned on when the powersource voltage is insufficient for the oscillating circuit to oscillate,the electronic timepiece can quickly starts running after the powergeneration is started.

In the electronic timepiece according to the present invention, it ispreferable that the switch circuit has a first switch that connects thefirst power source in parallel to the second power source and that, whenthe power source input detecting circuit detects that the second powersource is input, the control circuit turns on the first switch toconnect the first power source and the second power source. Theelectronic timepiece is configured to supply power to the clock circuitby detecting that the second power source is input, without providingthe second switch in parallel to the first switch.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a block configuration diagram of a rechargeable electronictimepiece according to a first embodiment of the present invention.

FIG. 2 is a block configuration diagram showing a modification of therechargeable electronic timepiece according to the first embodiment.

FIG. 3 is a block configuration diagram of a rechargeable electronictimepiece according to a second embodiment of the present invention.

FIG. 4 is a block configuration diagram showing a modification of therechargeable electronic timepiece according to the second embodiment.

FIG. 5 is a block configuration diagram of a rechargeable electronictimepiece according to a third embodiment of the present invention.

FIG. 6 is a block configuration diagram showing a modification of therechargeable electronic timepiece according to the third embodiment.

FIG. 7 is a block configuration diagram of a rechargeable electronictimepiece according to a fourth embodiment of the present invention.

FIG. 8 is a block configuration diagram showing a modification of therechargeable electronic timepiece according to the fourth embodiment.

FIG. 9 is a configuration diagram of power source input detecting meansand a switch control circuit according to the present invention.

FIG. 10 is a time chart of the operation of the power source inputdetecting means and the switch control circuit according to the presentinvention.

FIG. 11 is a block configuration diagram of a rechargeable electronictimepiece according to a fifth embodiment of the present invention.

FIG. 12 is a block configuration diagram showing a modification of therechargeable electronic timepiece according to the fifth embodiment.

FIG. 13 is a configuration diagram of power source input detecting meansand a second switch control circuit according to the present invention.

FIG. 14 is a diagram showing a relationship between an oscillation haltdetecting circuit 82 and a waveform shaping circuit 84.

FIG. 15 is a configuration diagram of a rechargeable electronictimepiece showing a conventional technique.

DETAILED DESCRIPTIONS

Rechargeable electronic timepiece according to embodiments of thepresent invention are explained in detail below.

FIG. 1 is a block diagram of a rechargeable electronic timepieceaccording to a first embodiment of the present invention. In FIG. 1,constituent elements similar to those shown in FIG. 15 are assigned withidentical reference numerals, and their explanation is omitted.

In FIG. 1, a reference numeral 86 denotes power source input detectingmeans that detects that the second storage means 3 is input to theelectronic timepiece, and 87 denotes a switch control circuit thatcontrols a switch 9 described later. The second storage means 3 suppliespower to the power source input detecting means 86 and the switchcontrol circuit 87. The switch 9 consists of a backward N-channeltransistor 91, and is connected in parallel to an N-channel transistor71 that constitutes a switch 7.

FIG. 9 shows one example of a circuit configuration of the power sourceinput detecting means 86 and the switch control circuit 87. The powersource input detecting means 86 includes a capacitor 861, a resistor862, and an inverter 863. One electrode of the capacitor 861 is set to aVDD potential, and the other electrode of the capacitor 861 is connectedto the resistor 862. One terminal of the resistor 862 is set to a VSSpotential, and the other terminal of the resistor 862 is set to thecapacitor 861. A line that connects between the capacitor 861 and theresistor 862 is connected to an input (a signal (a)) of the inverter863, and an output of the inverter 863 becomes an output (a signal (b))of the power source input detecting means 86.

The switch control circuit 87 includes a NAND latch 871 having NANDgates 8711 and 8712, and an inverter 872. An input of the NAND gate 8711of the NAND latch 871 is connected to the output (the signal (b)) of thepower source input detecting means 86. An input of the other NAND gate8712 is connected to an output (a signal (c)) of the oscillation haltdetecting circuit 82 according to the embodiment shown in FIG. 1. Anoutput of the NAND gate 8712 is connected to an input of the inverter872, and an output of the inverter 872 becomes an output (a signal (d))of the switch control circuit 87.

The operation of the circuit shown in FIG. 9 is explained with referenceto a time chart shown in FIG. 10. In FIG. 10, (a) to (d) show thesignals (a) to (d) respectively. A time t1 represents a time when apower source is input to the power source input detecting means 86, andalso a time when the second storage means 3 is connected to therechargeable clock. When the VSS potential is supplied to the powersource input detecting means 86, the capacitor 861 is charged to the VSSpotential based on a predetermined time according to the capacity of thecapacitor 861 and the resistance of the resistor 862. Therefore, thepotential of the signal (a) shown in FIG. 9 shifts to a level as shownin (a) in FIG. 10. When the potential of the input is higher than ½ VSS,the inverter 863 outputs an L level signal, and when the input is lowerthan ½ VSS, the inverter 863 outputs an H level signal.

A time t2 represents a time when the potential of the signal (a) becomes½ VSS. When the capacitor 861 is charged and also when the potential ofthe capacitor 861 becomes lower than ½ VSS (at time t2), the output (thesignal (b)) of the inverter 863 is switched from the L level to the Hlevel (refer to (b) in FIG. 10). As explained above, the power sourceinput detecting means 86 outputs the L level signal only at thebeginning when the second storage means 3 is input. When the secondstorage means 3 remains in the input state, the power source inputdetecting means 86 does not output the L level signal thereafter.

When an oscillation halt of the oscillating circuit 81 is detected, theoutput (the signal (c)) of the oscillation halt detecting circuit 82becomes the H level. Therefore, when the second storage means 3 isinput, the input (the signal (c)) of the NAND gate 8712 of the switchcontrol circuit 87 becomes the H level (refer to (c) in FIG. 10). Whenthe second storage means 3 is input, the signal (b) is at the L level.Therefore, the input (the signal (b)) of the NAND gate 8711 is at the Llevel, and accordingly, the output of the NAND gate 8711 becomes the Hlevel. Because both inputs are at the H level, the output of the NANDgate 8712 becomes the L level. At time t2, the NAND gate 8712 inputs theL level signal, and the output (the signal (d)) of the inverter 872becomes the H level (refer to (d)) in FIG. 10).

A time t3 represents a time when the oscillation halt detecting circuit82 detects the oscillation of the oscillating circuit 81. When theoscillation of the oscillating circuit 81 is detected, the output (thesignal (c)) of the oscillation halt detecting circuit 82 becomes the Llevel. At time t3, when the input (c) of the NAND gate 8712 becomes theL level, the output of the NAND gate 8712 becomes the H level. At timet3, the NAND gate 8712 inputs the H level signal, and the output (thesignal (d)) of the inverter 872 becomes the L level (refer to (d)) inFIG. 10). As explained above, the switch control circuit 87 outputs theH level signal after the second storage means 3 is input, based on theoutput (the signal (c)) of the power source input detecting circuit 86,and thereafter output the L level signal. When the second storage means3 remains in the input state, the switch control circuit 87 does notoperate thereafter.

The operation of the circuit shown in FIG. 1 is explained next.

As described above, the power consumption of the clock circuit 8 may betested in the middle of the assembly process in the plant. At thebeginning, the power generating means (i.e., the solar cell) 1 is notconnected to the circuit, and that the second storage means (i.e., thesecondary cell) 3 is not input to the electronic timepiece.

First, the second storage means 3 which is charged to some extent isinput.

Immediately before the second storage means 3 is input, the clockcircuit 8 is in the non-operating state. Because the oscillation haltdetecting circuit 82 is detecting the oscillation halt of theoscillating circuit 81, the signal (c) is at the H level. Because theoscillating circuit is in the oscillation halt state, the waveformshaping circuit 84 and the cell voltage detecting means 85 output the Llevel signals respectively.

FIG. 14 is a diagram showing a relationship between the oscillation haltdetecting circuit 82 and the waveform shaping circuit 84. In FIG. 14, adrain of an N-channel transistor 1401 is connected to each final outputof the waveform shaping circuit 84. A source bulk of the N-channeltransistor 1401 is connected to VSS, and a gate of this transistor isconnected to the oscillation halt detecting circuit 82. Upon detectingthe oscillation halt, the oscillation halt detecting circuit 82 suppliesthe H level signal to the gate of the N-channel transistor 1401. As aresult, the N-channel transistor 1401 is turned on, and each outputbecomes the VSS level. In other words, in the oscillation halt state,the waveform shaping circuit 84 and the cell voltage detecting means 85output the L level (i.e., the VSS level) signals. When the oscillatingcircuit 81 is oscillating, the oscillation halt detecting circuit 82outputs the L level signal, and the N-channel transistor 1401 is in theoff state. Therefore, the N-channel transistor 1401 does not affect thecircuit operation. Consequently, the switch 6 and the switch 7 become inthe off state. Because the switch control circuit 87 is outputting the Llevel signal at times other than when the second storage means 3 isinput, as described above, the switch 9 is also in the off state. Thefirst storage means 2 as the power source of the clock circuit 8 is alsoin the state of having no stored energy. Based on the above, immediatelybefore the second storage means 3 is input, the clock circuit 8 is inthe non-operating state, and the switch 6, the switch 7, and the switch9 are in the off state respectively.

When the second storage means 3 is input in this state, when detectingthat the second storage means 3 is input, the power source inputdetecting means 86 outputs the L level signal (i.e., the signal (b)), asdescribed above. When the signal (b) becomes the L level, the switchcontrol circuit 87 outputs the H level signal (i.e., the signal (d)). Asa result, the switch 9 is turned on. When the connected second storagemeans 3 is sufficiently charged and has sufficient voltage in advance,the energy stored in the second storage means 3 is charged to the firststorage means 2 via the switch 9 in the on state and a parasitic diodeof the forward N-channel transistor 72 of the switch 7. The voltage ofthe first storage means 2 rises due to the charging, and exceeds aminimum operating voltage of the oscillating circuit 81. Then, theoscillating circuit 81 starts oscillating, and the clock circuit 8starts operating.

As described above, when the oscillation halt detecting circuit 82detects that the oscillating circuit 81 starts oscillation, theoscillation halt detecting circuit 82 outputs the L level signal (i.e.,the signal (c)). When the signal (c) becomes the L level, the switchcontrol circuit 87 outputs the L level signal (i.e., the signal (d)). Asa result, the switch 9 is turned off. At the same time, when detectingthat the second storage means 3 has sufficient voltage, the cell voltagedetecting means 85 outputs the H level signal, and turns on the switch7. As explained above, when the second storage means 3 is input in thestate that the operation of the clock circuit 8 is halted, the clockcircuit 8 can quickly start operation. Therefore, the power consumptionof the clock circuit 8 can be tested easily. Needless to mention, thepresent system can be also employed at the time of disassembling theclock at a retail shop or the like.

FIG. 2 is a block configuration diagram showing a modification of therechargeable electronic timepiece according to the first embodiment. Therechargeable electronic timepiece shown in FIG. 2 is different from thatshown in FIG. 1 in that an OR circuit 92 is provided in place of theswitch 9 shown in FIG. 1. One input of the OR circuit 92 is connected tothe switch control circuit 87, and the other input of the OR circuit 92is connected to the cell voltage detecting means 85. An output of the ORcircuit 92 is connected to the gate of the N-channel transistor 71 ofthe switch 7.

In FIG. 2, as in the first embodiment, when detecting that the secondstorage means 3 is input, the power source input detecting circuit 86outputs the L level signal (i.e., the signal (b)). When the signal (b)becomes the L level, the switch control circuit 87 outputs the H levelsignal (i.e., the signal (d)). As a result, the OR circuit 92 outputsthe H level signal, and the N-channel transistor 71 of the switch 7 isturned on. Then, the energy stored in the second storage means 3 isdischarged to the first storage means 2 via the N-channel transistor 71of the switch 7 and the parasitic diode of the N-channel transistor 72of the switch 7. The voltage of the first storage means 2 rises due tothe charging, and exceeds the minimum operating voltage of theoscillating circuit 81. Then, the oscillating circuit 81 startsoscillating. Thereafter, when detecting that the oscillating circuit 81starts oscillation, the oscillation halt detecting circuit 82 outputsthe L level signal (i.e., the signal (c)), as in the first embodiment.When the signal (c) becomes the L level, the switch control circuit 87outputs the L level signal (i.e., the signal (d)). However, when itdetects that the second storage means 3 has a sufficient voltage, thecell voltage detecting means 85 outputs the H level signal. Therefore,the OR circuit 92 outputs the H level signal, and continues to keep theswitch 7 on. As explained above, when the second storage means 3 isinput in the state that the operation of the clock circuit 8 is halted,the clock circuit 8 can quickly start operation. As described above,when the OR circuit 92 is provided in place of the switch 9 shown inFIG. 1, the rechargeable electronic timepiece can operate in a similarmanner to that of the rechargeable electronic timepiece shown in FIG. 1.Needless to mention, the present modified system can be also employed atthe time of disassembling the clock at a retail shop or the like.

FIG. 3 is a block configuration diagram of a rechargeable electronictimepiece according to a second embodiment of the present invention. Therechargeable electronic timepiece shown in FIG. 3 is different from thatshown in FIG. 1 in that the switch control circuit 87 shown in FIG. 3 iscontrolled based on a signal of the frequency-dividing circuit 83.

According to the present embodiment, as in the first embodiment, it isassumed that, at the beginning, the power generating means 1 is notconnected to the circuit, and that the second storage means 3 is notinput to the electronic timepiece. Therefore, the second storage means 3is input first.

When it detects that the second storage means 3 is input, the powersource input detecting circuit 86 outputs the L level signal (i.e., thesignal (b)). When the signal (b) becomes the L level, the switch controlcircuit 87 turns on the switch 9. The energy stored in the secondstorage means 3 is discharged to the first storage means 2 via theN-channel transistor 91 of the switch 9 and the parasitic diode of theN-channel transistor 72 of the switch 7. The voltage of the firststorage means 2 rises due to the charging, and exceeds the minimumoperating voltage of the oscillating circuit 81. Then, the oscillatingcircuit 81 starts oscillating.

The frequency-dividing circuit 83 divides the frequency of the signaloutput from the oscillating circuit 81, and outputs the L level signal(i.e., the signal (c)) after a lapse of sufficient time. When the signal(c) becomes the L level, the switch control circuit 87 outputs the Llevel signal (i.e., the signal (d)). As a result, the switch 9 is turnedoff. Because the switch 9 is turned off after the oscillation of theoscillating circuit 81 is stabilized as described above, the clockcircuit 8 can operate more securely. In other words, even when theoscillating circuit 81 stops oscillation immediately after startingoscillation, the switch 9 is not immediately turned off. Therefore, thefirst storage means 2 is charged continuously. Consequently, theoscillating circuit 81 is urged to start oscillating again, therebyachieving the operation of the clock circuit more securely.

FIG. 4 is a block configuration diagram showing a modification of therechargeable electronic timepiece according to the second embodiment.The rechargeable electronic timepiece shown in FIG. 4 is different fromthat shown in FIG. 3 in that the OR circuit 92 is provided in place ofthe switch 9 shown in FIG. 3. One input of the OR circuit 92 isconnected to the switch control circuit 87, and the other input of theOR circuit 92 is connected to the cell voltage detecting means 85. Theoutput of the OR circuit 92 is connected to the gate of the N-channeltransistor 71 of the switch 7.

In FIG. 4, as in the second embodiment, when detecting that the secondstorage means 3 is input, the power source input detecting circuit 86outputs the L level signal (i.e., the signal (b)). When the signal (b)becomes the L level, the switch control circuit 87 outputs the H levelsignal (i.e., the signal (d)). As a result, the OR circuit 92 outputsthe H level signal, and the N-channel transistor 71 of the switch 7 isturned on. Then, the energy stored in the second storage means 3 isdischarged to the first storage means 2 via the N-channel transistor 71of the switch 7 and the parasitic diode of the N-channel transistor 72of the switch 7. The voltage of the first storage means 2 rises due tothe charging, and exceeds the minimum operating voltage of theoscillating circuit 81. Then, the oscillating circuit 81 startsoscillating.

The frequency-dividing circuit 83 divides the frequency of the signaloutput from the oscillating circuit 81, and outputs the L level signal(i.e., the signal (c)) after a lapse of sufficient time. When the signal(c) becomes the L level, the switch control circuit 87 outputs the Llevel signal (i.e., the signal (d)). However, when detecting that thesecond storage means 3 has a sufficient voltage, the cell voltagedetecting means 85 outputs the H level signal. Therefore, the OR circuit92 outputs the H level signal, and the N-channel transistor 71 of theswitch 7 is turned on. As described above, when the OR circuit 92 isprovided in place of the switch 9 shown in FIG. 3, the rechargeableelectronic timepiece can operate in a similar manner to that of therechargeable electronic timepiece shown in FIG. 3. Needless to mention,the present modified system can be also employed at the time ofdisassembling the clock at a retail shop or the like.

FIG. 5 is a block configuration diagram of a rechargeable electronictimepiece according to a third embodiment of the present invention. Therechargeable electronic timepiece shown in FIG. 5 is different from thatshown in FIG. 1 in that the switch control circuit 87 shown in FIG. 5 iscontrolled based on a signal of the power generating means 1.

According to the present embodiment, it is assumed that, at thebeginning, the power generating means 1 is built in the electronictimepiece, but the second storage means 3 is not input to the electronictimepiece. Therefore, the second storage means 3 is input first.

When detecting that the second storage means 3 is input, the powersource input detecting circuit 86 outputs the L level signal (i.e., thesignal (b)). When the signal (b) becomes the L level, the switch controlcircuit 87 turns on the switch 9. The energy stored in the secondstorage means 3 is discharged to the first storage means 2 via theN-channel transistor 91 of the switch 9 and the parasitic diode of theN-channel transistor 72 of the switch 7. The voltage of the firststorage means 2 rises due to the charging, and exceeds the minimumoperating voltage of the oscillating circuit 81. Then, the oscillatingcircuit 81 starts oscillating.

When the voltage of the second storage means 3 is insufficient, thevoltage of the first storage means 2 becomes lower than the minimumoperating voltage of the oscillating circuit 81, and the oscillatingcircuit 81 does not start oscillating accordingly. However, according tothe present embodiment, because the power generating means 1 is builtin, the power generating means starts oscillating. In FIG. 5, therechargeable electronic timepiece is configured such that the switchcontrol circuit 87 detects the power generation potential of the powergenerating means 1, and turns off the switch 9. When the switch 9 isoff, the first storage means 2 is separated from the second storagemeans 3, and the power generating means 1 charges the first storagemeans 2 using the power generating potential of the power generatingmeans 1.

When the first storage means 2 is sufficiently charged, the oscillatingcircuit 81 starts oscillating, and the clock circuit 8 starts operating.In this case, because the second storage means 3 does not have asufficient charge amount, the cell voltage detecting means 85 keeps theswitch 7 in the off state. Therefore, as explained with reference toFIG. 15, the first storage means 2 and the second storage means 3 arecharged alternately. After the second storage means 3 is sufficientlycharged, a state similar to that explained with reference to FIG. 15 isobtained. As explained above, even when the second storage means 3 hasinsufficient stored energy and also when the second storage means 3 hasinsufficient voltage, the oscillating circuit 81 can start normaloscillation based on the built-in power generating means 1. The presentembodiment is particularly effective at the time of disassembling andcleaning the electronic timepiece.

FIG. 6 is a block configuration diagram showing a modification of therechargeable electronic timepiece according to the third embodiment. Therechargeable electronic timepiece shown in FIG. 6 is different from thatshown in FIG. 5 in that the OR circuit 92 is provided in place of theswitch 9 shown in FIG. 5. One input of the OR circuit 92 is connected tothe switch control circuit 87, and the other input of the OR circuit 92is connected to the cell voltage detecting means 85. The output of theOR circuit 92 is connected to the gate of the N-channel transistor 71 ofthe switch 7.

In FIG. 6, as in the third embodiment, when detecting that the secondstorage means 3 is input, the power source input detecting circuit 86outputs the L level signal (i.e., the signal (b)). When the signal (b)becomes the L level, the switch control circuit 87 outputs the H levelsignal (i.e., the signal (d)). As a result, the OR circuit 92 outputsthe H level signal, and the N-channel transistor 71 of the switch 7 isturned on. Then, the energy stored in the second storage means 3 isdischarged to the first storage means 2 via the N-channel transistor 71of the switch 7 and the parasitic diode of the N-channel transistor 72of the switch 7. The voltage of the first storage means 2 rises due tothe charging, and exceeds the minimum operating voltage of theoscillating circuit 81. Then, the oscillating circuit 81 startsoscillating.

When the voltage of the second storage means 3 is insufficient, thevoltage of the first storage means 2 becomes lower than the minimumoperating voltage of the oscillating circuit 81, and the oscillatingcircuit 81 does not start oscillating accordingly. However, according tothe present embodiment, because the power generating means 1 is builtin, the power generating means starts oscillating. As in the thirdembodiment, the switch control circuit 87 detects the power generationpotential of the power generating means 1, and outputs the L levelsignal. As a result, the OR circuit 92 outputs the L level signal, andturns off the N-channel transistor 71 of the switch 7. When the switch 7is off, the first storage means 2 is separated from the second storagemeans 3, and the power generating means 1 charges the first storagemeans 2 using the power generating potential of the power generatingmeans 1.

When the first storage means 2 is sufficiently charged, the oscillatingcircuit 81 starts oscillating, and the clock circuit 8 starts operating.In this case, because the second storage means 3 does not have asufficient charge amount, the cell voltage detecting means 85 outputsthe L level signal. Therefore, the OR circuit 92 keeps outputting the Llevel signal, and the switch 7 remains in the off state. As a result, asexplained with reference to FIG. 14, the first storage means 2 and thesecond storage means 3 are charged alternately. After the second storagemeans 3 is sufficiently charged, a state similar to that explained withreference to FIG. 14 is obtained. As explained above, because the powergenerating means 1 is built in, even when the second storage means 3 hasinsufficient stored energy and also when the second storage means 3 hasinsufficient voltage, the power generating means 1 can charge the firststorage means 2 without charging the second storage means 3 even if thecharge of the second storage means 3 is not sufficient. Consequently,the clock circuit 8 can be started quickly. As shown in FIG. 6, when theOR circuit 92 is provided in place of the switch 9 shown in FIG. 5, therechargeable electronic timepiece can operate in a similar manner tothat of the rechargeable electronic timepiece shown in FIG. 5. Needlessto mention, the present modified system can be also employed at the timeof disassembling the clock at a retail shop or the like.

FIG. 7 is a block configuration diagram of a rechargeable electronictimepiece according to a fourth embodiment of the present invention. InFIG. 7, constituent elements similar to those shown in FIG. 1 areassigned with identical reference numerals, and their explanation isomitted. The rechargeable electronic timepiece shown in FIG. 7 isdifferent from that shown in FIG. 1 in that a comparator circuit 100 isprovided in FIG. 7.

In FIG. 7, the comparator circuit 100 consists of a buffer gate 101, adiode 102, and a pull-down resistor 103. The diode 102 is configuredsuch that its VF is larger than the operation starting voltage of theoscillating circuit 81. An anode of the diode 102 is connected to theoutput of the switch control circuit 87, and a cathode of the diode 102is connected to the input of the buffer gate 101. The input of thebuffer gate 101 is pulled down to the minus side of the second storagemeans 3 by the pull-down resistor 103. An output of the buffer gate 101is connected to the gate of the N-channel transistor 91 of the switch 9.

The operation of the rechargeable electronic timepiece shown in theblock configuration diagram of FIG. 7 is explained next. According tothe present embodiment, it is assumed that the power generating means 1is built in the electronic timepiece, but the second storage means 3 isnot input to the electronic timepiece in advance. Like in the aboveembodiments, when the clock circuit 8 is not operating, and when theswitch 6, the switch 7, and the switch 9 are in the off state, thesecond storage means 3 is input.

As in the first embodiment, when detecting that the second storage means3 is input, the power source input detecting circuit 86 outputs the Llevel signal (i.e., the signal (b)). As a result, the switch controlcircuit 87 outputs the H level signal (i.e., the signal (d)).

When a difference (that is, the power source voltage of the secondstorage means 3) between the H level of the output (i.e., the signal(d)) of the switch control circuit 87 and a potential at the minus sideof the second storage means 3 does not exceed the VF of the diode 102due to the diode 102 connected between the switch control circuit 87 andthe switch 9, the output of the diode 102 becomes in the release state.In this case, the input of the buffer gate 101 is fixed to the L levelby the pull-down resistor 103, the output of the buffer gate 101 is atthe L level, and the switch 9 remains in the off state. On the otherhand, when the power source voltage of the second storage means 3exceeds the VF of the diode 102, the output of the diode 102 becomes theH level, the output of the buffer gate 101 also becomes the H level, andthe switch 9 is turned on.

When the switch 9 is turned on, the energy stored in the second storagemeans 3 is discharged to the first storage means 2 via the switch 9 andthe parasitic diode of the N-channel transistor 72 of the switch 7, asdescribed above. The voltage of the first storage means 2 rises due tothe charging, and exceeds the minimum operating voltage of theoscillating circuit 81. Then, the oscillating circuit 81 startsoscillating, and the clock circuit 8 starts operating.

The switch 9 is turned on only when the voltage of the second storagemeans 3 exceeds the operation starting voltage of the oscillatingcircuit 81. Therefore, when the switch 9 is turned on, the oscillatingcircuit 81 can oscillate without fail. Accordingly, the switch 9 is notturned on when the voltage of the second storage means 3 is notsufficient to oscillate the oscillating circuit 81 even though thesecond storage means 3 is connected.

In this case, when the connected power generating means 1 is generatingpower, the power generating means 1 can store energy into the firststorage means 2. As described above, when the voltage of the secondstorage means 3 is insufficient, the switch 9 is not turned on. Further,the cell voltage detecting means 85 does not turn on the switch 7.Accordingly, the energy stored in the first storage means 2 is notcharged to the second storage means 3, thereby quickly charging thefirst storage means 2. When the first storage means 2 is sufficientlycharged, the oscillating circuit 81 can start oscillating, therebyoperating the clock circuit 8.

FIG. 8 is a block configuration diagram showing a modification of therechargeable electronic clock according to the fourth embodiment. Therechargeable electronic timepiece shown in FIG. 8 is different from thatshown in FIG. 7 in that the OR circuit 92 is provided in place of theswitch 9 shown in FIG. 7. One input of the OR circuit 92 is connected tothe output of the buffer gate 101 of the comparator circuit 100, and theother input of the OR circuit 92 is connected to the cell voltagedetecting means 85. The output of the OR circuit 92 is connected to thegate of the N-channel transistor 71 of the switch 7.

In FIG. 8, as in the fourth embodiment, when detecting that the secondstorage means 3 is input, the power source input detecting circuit 86outputs the L level signal (i.e., the signal (b)). When the signal (b)becomes the L level, the switch control circuit 87 outputs the H levelsignal (i.e., the signal (d)).

As described above, the comparator circuit 100 outputs the L levelsignal when the power source voltage of the second storage means 3 doesnot exceed the VF of the diode 102. When the power source voltage of thesecond storage means 3 exceeds the VF of the diode 102, the comparatorcircuit 100 outputs the H level signal.

When the comparator circuit 100 outputs the H level signal, the ORcircuit 92 outputs the H level signal, and turns on the N-channeltransistor 71 of the switch 7. Then, the energy stored in the secondstorage means 3 is discharged to the first storage means 2 via thetransistor 71 of the switch 7 and the parasitic diode of the N-channeltransistor 72 of the switch 7. The voltage of the first storage means 2rises due to the charging, and exceeds the minimum operating voltage ofthe oscillating circuit 81. Then, the oscillating circuit 81 startsoscillating and the clock circuit 8 starts operating.

The N-channel transistor 71 of the switch 7 is turned on only when thevoltage of the second storage means 3 exceeds the operation startingvoltage of the oscillating circuit 81. Therefore, when the N-channeltransistor 71 of the switch 7 is turned on, the oscillating circuit 81can oscillate without fail. Accordingly, the N-channel transistor 71 ofthe switch 7 is not turned on, when the voltage of the second storagemeans 3 is not sufficient to oscillate the oscillating circuit 81although the second storage means 3 is connected. In this case, it isnecessary to connect the power generating means 1 to generate power, andstore the generated energy into the first storage means 2. As describedabove, when the first storage means 2 is sufficiently charged, theoscillating circuit 81 can start oscillating, thereby operating theclock circuit 8.

As described above, when the OR circuit 92 is provided in place of theswitch 9 shown in FIG. 7, the rechargeable electronic timepiece canoperate in a similar manner to that of the rechargeable electronictimepiece shown in FIG. 7. Needless to mention, the present modifiedsystem can be also employed at the time of disassembling the clock at aretail shop or the like.

FIG. 11 is a block configuration diagram of a rechargeable electronictimepiece according to a fifth embodiment of the present invention. InFIG. 11, constituent elements similar to those shown in FIG. 1 areassigned with identical reference numerals, and their explanation isomitted. The rechargeable electronic timepiece shown in FIG. 11 isdifferent from that shown in FIG. 1 in that a second switch controlcircuit 88 is used in FIG. 11.

FIG. 13 shows one example of a circuit configuration of the power sourceinput detecting means 86 and the second switch control circuit 88. As inFIG. 9, the power source input detecting means 86 includes the capacitor861, the resistor 862, and the inverter 863. One electrode of thecapacitor 861 is set to the VDD potential, and the other electrode ofthe capacitor 861 is connected to the resistor 862. One terminal of theresistor 862 is set to the VSS potential, and the other terminal of theresistor 862 is set to the capacitor 861. The line that connects betweenthe capacitor 861 and the resistor 862 is connected to the input (i.e.,the signal (a)) of the inverter 863, and the output of the inverter 863becomes the output (i.e., the signal (b)) of the power source inputdetecting means 86.

The second switch control circuit 88 consists of a CR oscillator 881,and a counter 882. The CR oscillator 881 includes inverters 8811, 8813,and 8814, a NAND gate 8812, a NAND gate 8717, a resistor 8815, and acapacitor 8816. The counter 882 includes a timer 8821, and an inverter8822.

The CR oscillator 881 starts oscillating when the input signal (i.e.,the signal (d)) becomes the H level. A frequency of the output (i.e., asignal (e)) is changed according to a time constant determined by theresistor 8815 and the capacitor 8816. The counter 882 as one example ofclock means counts the output (i.e., the signal (e)) of the CRoscillator. When the counter 882 counts up (N times), the counteroutputs the L level signal (i.e., the signal (d)).

The operation of the circuit shown in FIG. 13 is explained next. Thepotential of the signal (a) of the power source input detecting means 86shifts as shown by (a) in FIG. 10. Therefore, when the second storagemeans 3 is input, the output (i.e., the signal (b)) of the power sourceinput detecting means 86 is at the L level. The timer 8821 of thecounter 882 is reset by the signal (b), and the output signal of thetimer 8821 becomes the L level. The inverter 8822 changes the output(i.e., the signal (d)) of the counter 882 to the H level. When thesignal (d) becomes the H level, the CR oscillator 881 startsoscillating. The counter 882 counts the output (i.e., the signal (e)) ofthe CR oscillator 881. When the count reaches a predetermined countnumber (N), the counter 882 outputs the L level (i.e., the signal (d)).When the signal (d) becomes the L level, the CR oscillator 881 stopsoscillating.

It is desirable that the time taken for the output of the second switchcontrol circuit 88, or the output (i.e., the signal (d)) of the counter882, to reach from the H level to the L level after the second storagemeans 3 is input, is larger than the time taken for the first storagemeans 2 to be charged by the second storage means 3 until theoscillation of the oscillating circuit 81 is stabilized. It is alsodesirable that the time taken for the output of the second switchcontrol circuit 88 to reach from the H level to the L level is the timetaken for the cell voltage detecting means 85 to start operating. Thetime taken for the output of the second switch control circuit 88 toreach from the H level to the L level can be changed by changing thetime constant of the CR oscillator 882 or by changing the count-upnumber (N) of the counter 882.

The operation of the rechargeable electronic timepiece shown in theblock configuration diagram of FIG. 11 is explained next. According tothe present embodiment, it is assumed that the power generating means 1is built into the electronic timepiece, but the second storage means 3is not input to the electronic timepiece in advance. As in the aboveembodiments, when the clock circuit 8 is not operating, and when theswitch 6, the switch 7, and the switch 9 are in the off state, thesecond storage means 3 is input.

As in the first embodiment, when detecting that the second storage means3 is input, the power source input detecting circuit 86 outputs the Llevel signal (i.e., the signal (b)). When the signal (b) becomes the Llevel, the second switch control circuit 88 outputs the H level signal(i.e., the signal (d)).

When the second switch control circuit 88 outputs the H level signal(i.e., the signal (d)), the switch 9 is turned on. When the connectedsecond storage means 3 is sufficiently charged and has sufficientvoltage in advance, the energy stored in the second storage means 3 ischarged to the first storage means 2 via the switch 9 in the on stateand the parasitic diode of the forward N-channel transistor 72 of theswitch 7. The voltage of the first storage means 2 rises due to thecharging, and exceeds the minimum operating voltage of the oscillatingcircuit 81. Then, the oscillating circuit 81 starts oscillating, and theclock circuit 8 starts operating.

As described above, the second switch control circuit 88 outputs the Llevel (i.e., the signal (d)), after a lapse of time determined inadvance based on the time constant of the CR oscillator 881 and thecount up number (N) of the counter 882. As a result, the switch 9 isturned off. At the same time, when detecting that there is sufficientvoltage of the second storage means 3, the cell voltage detecting means85 outputs the H level signal, and turns on the switch 7. As explainedabove, when the second storage means 3 is input in the state that theoperation of the clock circuit 8 is halted, the clock circuit 8 canquickly start operation. Therefore, the power consumption of the clockcircuit 8 can be tested easily. Needless to mention, the present systemcan be also employed at the time of disassembling the clock at a retailshop or the like.

In this case, the operation of the second switch control circuit 88 doesnot depend on whether the oscillating circuit 81 is oscillating or not.Therefore, after the second storage 3 is input, even when the voltage ofthe second storage means 3 is low and when the oscillating circuit 81does not start oscillating, the output (i.e., the signal (d)) of thesecond switch control circuit 88 becomes the L level, and turns off theswitch 9. Accordingly, when the power generating means (i.e., the solarpanel) 1 starts generating power upon the incidence of light onto thepower generating means, the first storage means 2 is charged to enablethe oscillating circuit 81 to start oscillating.

FIG. 12 is a block configuration diagram showing a modification of therechargeable electronic timepiece according to the fifth embodiment. Therechargeable electronic timepiece shown in FIG. 12 is different fromthat shown in FIG. 11 in that the OR circuit 92 is provided in place ofthe switch 9 shown in FIG. 11. One input of the OR circuit 92 isconnected to the second switch control circuit 88, and the other inputof the OR circuit 92 is connected to the cell voltage detecting means85. The output of the OR circuit 92 is connected to the gate of theN-channel transistor 71 of the switch 7.

In FIG. 12, as in the fifth embodiment, when detecting that the secondstorage means 3 is input, the power source input detecting circuit 86outputs the L level signal (i.e., the signal (b)). When the signal (b)becomes the L level, the second switch control circuit 88 outputs the Hlevel signal (i.e., the signal (d)). The OR circuit 92 outputs the Hlevel signal, and the N-channel transistor 71 of the switch 7 is turnedon. Then, the energy stored in the second storage means 3 is dischargedto the first storage means 2 via the N-channel transistor 71 of theswitch 7 and the parasitic diode of the N-channel transistor 72 of theswitch 7. The voltage of the first storage means 2 rises due to thecharging, and exceeds the minimum operating voltage of the oscillatingcircuit 81. Then, the oscillating circuit 81 starts oscillating. Asdescribed above, when the OR circuit 92 is provided in place of theswitch 9 shown in FIG. 11, the rechargeable electronic timepiece canoperate in a similar manner to that of the rechargeable electronictimepiece shown in FIG. 11. Needless to mention, the present modifiedsystem can be also employed at the time of disassembling the clock at aretail shop or the like.

1. An electronic timepiece comprising: a first power source; a clock circuit connected to the first power source; a power source input detecting circuit; a switch circuit for connecting the first power source and a second power source whose capacity is larger than a capacity of the first source, wherein the switch circuit is in an off state during a halted state of the clock circuit; and a control circuit for, in response to the power source input detecting circuit detecting the insertion of the second power source during a halted state of the clock circuit, controlling the switch circuit to turn on in order to connect the first power source and the second power source so that the first power source is charged by the second power source, thereby operating the clock circuit.
 2. The electronic timepiece according to claim 1, wherein the switch circuit has a first switch that connects the first power source and the second power source in parallel, and a second switch that is connected in parallel to the first switch, and when the power source input detecting circuit detects the input of the second power source, the control circuit turns on the second switch to connect the first power source and the second power source.
 3. The electronic timepiece according to claim 2, further comprising: a power generator; and a voltage detector for turning on the first switch when the power generator sufficiently charges the second power source.
 4. The electronic timepiece according to claim 2, wherein the control circuit is controlled by the clock circuit to turn off the second switch when a predetermined condition is detected after the second switch was turned on.
 5. The electronic timepiece according to claim 4, wherein the clock circuit has an oscillating circuit, and the predetermined condition is that the oscillating circuit starts oscillating.
 6. The electronic timepiece according to claim 4, wherein the predetermined condition is a lapse of a predetermined time after the second switch was turned on.
 7. The electronic timepiece according to claim 4, wherein the control circuit includes clocking means, and the predetermined condition is that the clocking means runs for a predetermined time.
 8. The electronic timepiece according to claim 4, wherein the predetermined condition is a lapse of a constant time after the oscillating circuit starts oscillating after the second switch was turned on.
 9. The electronic timepiece according to claim 4, further comprising a power generator, wherein the predetermined condition is that the power generator means generates power.
 10. The electronic timepiece according to claim 2, further comprising a comparator circuit that operates so as not to turn on the second switch when the voltage of the second power source is at or below a predetermined voltage.
 11. The electronic timepiece according to claim 1, wherein the switch circuit has a first switch that connects the first power source in parallel to the second power source and, when the power source input detecting circuit detects that the second power source is input, the control circuit turns on the first switch to connect the first power source and the second power source.
 12. The electronic timepiece according to claim 11, further comprising: a power generator; and a voltage detector for turning on the first switch when the power generator sufficiently charges the second power source.
 13. The electronic timepiece according to claim 11, wherein the control circuit is controlled by the clock circuit to keen the first switch in the ON state until a predetermined condition is detected after the first switch was turned on.
 14. The electronic timepiece according to claim 13, wherein the clock circuit has an oscillating circuit, and the predetermined condition is that the oscillating circuit starts oscillating.
 15. The electronic timepiece according to claim 13, wherein the predetermine condition is a lapse of a predetermined time has passed after the first switch was turned on.
 16. The electronic timepiece according to claim 13, wherein the control circuit includes clocking means, and the predetermined condition is that the clocking means runs for a predetermined time.
 17. The electronic timepiece according to claim 13, wherein the predetermined condition is a lapse of a constant time has passed after the oscillating circuit starts oscillating after the first switch was turned on.
 18. The electronic timepiece according to claim 13, further comprising a power generator, wherein the predetermined condition is that the power generator generates power after the first switch was turned on.
 19. The electronic timepiece according to claim 11, further comprising a comparator circuit that operates so as not to turn on the first switch when the voltage of the second power source is at or below a predetermined voltage. 